1. Field of the Invention
The present invention relates to a technique of applying an accelerated stress to a cell transistor of a semiconductor memory to ensure the reliability of a gate insulator of the cell transistor. The present invention relates particularly to a semiconductor memory device used in a dynamic random access memory (RAM) (referred to as a DRAM hereinafter) in which a boost voltage is applied to word lines, and a static random access memory (referred to as an SRAM).
2. Description of the Related Art
A screening test to eliminate devices which inherently include a defect has been conventionally performed in order to ensure the reliability of a semiconductor device. The screening test mainly includes methods for accelerating an electric field and for accelerating a temperature. A burn-in method capable of simultaneously achieving the acceleration of an electric field and that of a temperature is frequently used as the screening test. The burn-in method is effective in a device having a possibility of malfunctioning in the earlier stage of its usage.
In the screening test of a semiconductor memory device using the burn-in method, word lines are sequentially accessed by address input. Therefore, when the word lines are sequentially accessed during the burn-in operation, a cell transistor connected to a word line receives a stress (more precisely the maximum stress) less frequently than a transistor of a peripheral circuit does.
For example, the number of word lines of a 4 mega bit (4 mb) DRAM is 4096, and the number of word lines which are selected in one cycle from among the 4096 word lines, is only four. Access to all cell transistors is thus completed in 1024 cycles. In other words, the time for which a stress is applied to the cell transistor is only 1/1024 the time for which a stress is applied to the transistor of the peripheral circuit. This type of screening test is not advantageous since it does not efficiently and quickly test for a defective cell transistor and it may degrade peripheral circuitry.
In recent DRAMs, generally, a Vcc/2 voltage which is a half of a power source voltage, is applied to a capacitor electrode of a memory cell. The electric field on the capacitor insulation film is weak so that, even though the insulation film is thin, it is usually reliable. However, the electric field is strong on the gate oxide film of a transistor to which a boosted voltage (e.g., around 1.5 Vcc) is applied so that, even though the oxide film is thick, it is more likely to be unreliable. Therefore, the transistor to which the boosted voltage is applied, especially needs to undergo the screening test however, it is a cell transistor and, as described above, the efficiency of the screening test is only 1/1024.